The present invention generally relates to semiconductor structures, and more particularly to field effect transistor (FET) devices including FinFET devices having strained channel regions, and methods for making the same.
Complementary metal-oxide-semiconductor (CMOS) technology is commonly used for fabricating FETs as part of advanced integrated circuits (IC), such as CPUs, memory, storage devices, and the like. As integrated circuits continue to scale downward in size, there is a growing need in CMOS technology to achieve higher device density without affecting performance and/or reliability while keeping production costs down.
With the aim of increasing device density, fin field effect transistors (FinFETs), or tri-gate structures, are becoming more widely used, primarily because FinFETs may offer better performance than planar FETs at the same power budget. FinFETs are three dimensional (3-D), fully depleted metal-oxide semiconductor field effect transistor (MOSFET) devices representing an important part of CMOS fabrication technology to create microelectronic devices with ever-decreasing dimensions.
FinFETs may have a fin structure formed from a semiconductor substrate material. The fin may form a channel region located between a source region and a drain region. A gate structure may be located over the fin enfolding the channel region. Such architecture allows for a more precise control of the conducting channel by the gate, significantly reducing the amount of current leakage when the device is in off state.
Channel straining techniques are commonly used in CMOS manufacturing to enhanced carrier mobility in the channel region. Based on the type of carrier and the direction of the stress applied, the carrier mobility within the channel region may be enhanced or reduced. For example, in a p-type FET (p-FET), applying a compressive stress to the channel region may increase hole mobility while reducing electron mobility, this in turn may improve the performance of p-FET devices. Similarly, in an n-type FET (n-FET), applying a tensile stress to the channel region may increase electron mobility while reducing hole mobility, this in turn may improve the performance of n-FET devices.